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41 dB Range, 1 dB Step Size, Programmable Dual VGA AD8372
FEATURES
Dual independent digitally controlled VGA Differential input and output 150 differential input Open-collector differential output 7.8 dB noise figure to 100 MHz @ maximum gain HD2/HD3 better than 77 dBc for 1 V p-p differential output -3 dB bandwidth of 150 MHz 41 dB gain range 1 dB step size 0.2 dB Serial 8-bit bidirectional SPI control interface Wide input dynamic range Pin-programmable output stage Power-down feature Single 5 V supply: 106 mA per channel 32-lead LFCSP, 5 mm x 5 mm package
ENB1 IPC1 INC1 RXT2 CLK1 SDO1 SDI1 LCH1 REGISTERS AND GAIN DECODER CHANNEL 1 POSTAMP
FUNCTIONAL BLOCK DIAGRAM
AD8372
REF2 OPC1 ONC1 RXT2 CLK2 SDO2 SDI2 LCH2
IPC2 INC2 REF1 CHANNEL 2 POSTAMP
OPC2
07051-001
ONC2 ENB2
Figure 1.
APPLICATIONS
Differential ADC drivers CMTS upstream direct sampling receivers CATV modem signal scaling Generic RF/IF gain stages Single-ended-to-differential conversion
GENERAL DESCRIPTION
The AD8372 is a dual, digitally controlled, variable gain amplifier that provides precise gain control, high IP3, and low noise figure. The excellent distortion performance and moderate signal bandwidth make the AD8372 a suitable gain control device for a variety of multichannel receiver applications. For wide input dynamic range applications, the AD8372 provides a broad 41 dB gain range. The gain is programmed through a bidirectional 4-pin serial interface. The serial interface consists of a clock, latch, data input, and data output lines for each channel. The AD8372 provides the ability to set the transconductance of the output stage using a single external resistor. The RXT1 and RXT2 pins provide a band gap derived stable reference voltage of 1.56 V. Typically 2.0 k shunt resistors to ground are used to set the maximum gain to a nominal value of 31 dB. The current setting resistors can be adjusted to manipulate the gain and distortion performance of each channel. This is a flexible feature in applications where it is desirable to trade off distortion performance for lower power consumption. The AD8372 is powered on by applying the appropriate logic level to the ENB1, ENB2 pins. When powered down, the AD8372 consumes less than 2.6 mA and offers excellent input-to-output isolation. The gain setting is preserved when powered down. Fabricated on an Analog Devices high frequency BiCMOS process, the AD8372 provides precise gain adjustment capabilities with good distortion performance. The quiescent current of the AD8372 is typically 106 mA per channel. The AD8372 amplifier comes in a compact, thermally enhanced 5 mm x 5 mm 32-lead LFCSP package and operates over the temperature range of -40C to +85C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved.
AD8372 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Serial Control Interface Timing ................................................. 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ..............................................8 Theory of Operation ...................................................................... 10 Single-Ended and Differential Signals..................................... 10 Passive Filter Techniques........................................................... 10 Digital Gain Control .................................................................. 10 Driving Analog-to-Digital Converters.................................... 10 Evaluation Board Schematic ......................................................... 12 Outline Dimensions ....................................................................... 13 Ordering Guide .......................................................................... 13
REVISION HISTORY
11/07--Revision 0: Initial Version
Rev. 0 | Page 2 of 16
AD8372 SPECIFICATIONS
VS = 5 V, T = 25C, ZS = 150 , ZL = 250 at 35 MHz, 1 V p-p differential output, RXT1 = RXT2 = 2.0 k, unless otherwise noted. Table 1.
Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth INPUT STAGE Maximum Input Swing at Each Input Pin Input Resistance Common-Mode Input Voltage CMRR GAIN Maximum Voltage Gain Minimum Voltage Gain Gain Step Size Gain Step Accuracy Gain Flatness Gain Temperature Sensitivity Step Response OUTPUT STAGE Output Voltage Swing Output Resistance Channel Isolation NOISE/HARMONIC PERFORMANCE 5 MHz Noise Figure Second Harmonic Third Harmonic Output IP3 Output 1 dB Compression Point 35 MHz Noise Figure Second Harmonic Third Harmonic Output IP3 Output 1 dB Compression Point 65 MHz Noise Figure Second Harmonic Third Harmonic Output IP3 Output 1 dB Compression Point 85 MHz Noise Figure Second Harmonic Third Harmonic Output IP3 Output 1 dB Compression Point Conditions VOUT < 1 V p-p, CLOAD < 3pF Pin IPCI, Pin INC1, Pin IPC2, and Pin INC2 Differential Gain code = 1x101010 (max gain) Gain code = 1x101010 Gain code = 1x000001 From gain code 1x000001 to 1x101010 From gain code 1x000001 to 1x101010 Gain code = 1x101010, from 5 MHz to 65MHz Gain code = 1x101010 For 6 dB gain step, 10% settling Pin OPCI, Pin ONC1, Pin OPC2, and Pin ONC2 At P1dB, gain code = 1x101010 Differential Measured at differential output for differential input applied to alternate channel Gain code = 1x101010 (max gain) 7.8 79 91 32 18.2 Gain code = 1x101010 (max gain) 7.8 79 87 35 18.1 Gain code = 1x101010 (max gain) 7.9 78 85 35 17.9 Gain code = 1x101010 8.1 77 85 35 17.7 dB dBc dBc dBm dBm dB dBc dBc dBm dBm dB dBc dBc dBm dBm dB dBc dBc dBm dBm Min Typ 130 5 150 2.4 55 32 -9 1.0 0.3 0.7 7.5 20 9 3.5 55 Max Unit MHz V p-p V dB dB dB dB dB dB mdB/C ns V p-p k dB
Rev. 0 | Page 3 of 16
AD8372
Parameter POWER INTERFACE Supply Voltage Quiescent Current per Channel vs. Temperature Power-Down Current, Both Channels vs. Temperature ENABLE INTERFACE Enable Threshold ENB1, ENB2 Input Bias Current GAIN CONTROL INTERFACE VIH Input Bias Current Serial Port Output Feedthrough Conditions Min 4.5 Thermal connection made to exposed paddle under device -40C TA +85C ENB1 and ENB2 low -40C TA +85C Pin ENB1 and Pin ENB2 Minimum voltage to enable the device ENB1, ENB2 = 0 V Pin CLK1, Pin CLK2, Pin SDI1, Pin SDI2, Pin SDO1, Pin SDO2, Pin LCH1, and Pin LCH2 Minimum voltage for a logic high Worse-case feedthrough from CLK1, CLK2, SDI1, SDI2, SDO1, SDO2, LCH1, LCH2 to OPC1 and ONC2, or OPC2 and ONC2 106 135 1.2 1.3 0.8 400 Typ Max 5.5 Unit V mA mA mA mA V nA
2.4 400 -60
V nA dB
Table 2. Gain Code vs. Voltage Gain Look-Up Table
8-Bit Binary Gain Code 1 RW DC 000000 RW DC 000001 RW DC 000010 RW DC 000011 RW DC 000100 RW DC 000101 RW DC 000110 RW DC 000111 RW DC 001000 RW DC 001001 RW DC 001010 RW DC 001011 RW DC 001100 RW DC 001101 RW DC 001110 RW DC 001111 RW DC 010000 RW DC 010001 RW DC 010010 RW DC 010011 RW DC 010100 RW DC 010101
1
Voltage Gain (dB) < -60 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11
8-Bit Binary Gain Code 1 RW DC 010110 RW DC 010111 RW DC 011000 RW DC 011001 RW DC 011010 RW DC 011011 RW DC 011100 RW DC 011101 RW DC 011110 RW DC 011111 RW DC 100000 RW DC 100001 RW DC 100010 RW DC 100011 RW DC 100100 RW DC 100101 RW DC 100110 RW DC 100111 RW DC 101000 RW DC 101001 RW DC 101010 RW DC 101011
Voltage Gain (dB) +12 +13 +14 +15 +16 +17 +18 +19 +20 +21 +22 +23 +24 +25 +26 +27 +28 +29 +30 +31 +32 < -60
RW is the Read/Write bit, RW = 0 for read mode, RW = 1 for write mode. DC is the Don't Care bit.
Rev. 0 | Page 4 of 16
AD8372
SERIAL CONTROL INTERFACE TIMING
tCLK
CLK1 OR CLK2
tPW tLH
tLS
LCH1 OR LCH2
tDS
SDI1 OR SDI2
tDH
DON'T CARE LSB LSB + 1 LSB + 2 MSB - 2 MSB - 1 MSB
WRITE BIT
Figure 2. Write Mode Timing Diagram
tD
CLK1 OR CLK2
tCLK
tPW
tLH
tLS
LCH1 OR LCH2
tDS
SDI1 OR SDI2 SDO1 OR SDO2
tDH
DC LSB DC LSB + 1 DC LSB + 2 DC MSB - 2 DC MSB - 1 DC MSB
07051-004
READ BIT
DC
NOTES 1. THE GAIN WORD BIT IS UPDATED AT THE SDO PIN ON THE FALLING CLOCK EDGE.
Figure 3. Read Mode Timing Diagram
Table 3. Serial Programming Timing Parameters
Parameter Clock Pulse Width (tPW) Clock Period (tCK) Write Mode Setup Time Data vs. Clock (tDS) Hold Time Data vs. Clock (tDH) Setup Time Latch vs. Clock (tLS) Hold Time Latch vs. Clock (tLH) Read Mode Clock to Data Out (tD) Min 10 20 0.0 1.6 -1.8 2.0 4.5 Unit ns ns ns ns ns ns ns
Rev. 0 | Page 5 of 16
07051-003
NOTES 1. THE FIRST SDI BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL GAIN WORD REGISTER. FOR A WRITE OPERATION, THE FIRST BIT SHOULD BE A HIGH LOGIC LEVEL, FOR A READ OPERATION THE FIRST BIT SHOULD BE A LOGIC 1. THE GAIN WORD BIT IS THEN REGISTERED INTO THE SDI PIN ON THE NEXT RISING CLOCK.
AD8372 ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Supply Voltage, VS ENB1, ENB2, SDI1, SDI2, SDO1, SDO2, CLK1, CLK2, LCH1, LCH2 Differential Input Voltage, VIPC1 - VINC1, VIPC2 - VINC2 Internal Power Dissipation JA (Exposed Paddle Soldered Down) JC (At Exposed Paddle) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range
1 2
Rating 5.5 V VS + 500 mV V p-p 1.4 W 34.6C/W1, 2 3.6C/W2 150C -40C to +85C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Still air. All values are modeled using a standard 4-layer JEDEC test board with the pad soldered to the board and thermal vias in the board.
Rev. 0 | Page 6 of 16
AD8372 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
32 31 30 29 28 27 26 25
24 23 22 21 20 19 18 17
DGD1 INC1 IPC1 REF1 RXT1 AGD1 ENB1 AVS1
DVS1 LCH1 SDI1 CLK1 CLK2 SDI2 LCH2 DVS2
1 2 3 4 5 6 7 8
PIN 1 INDICATOR
TOP VIEW (Not to Scale)
AD8372
OPC1 ONC1 AGD1 SDO1 SDO2 AGD2 ONC2 OPC2
9 10 11 12 13 14 15 16
Figure 4. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Mnemonic DVS1 LCH1 SDI1 CLK1 CLK2 SDI2 LCH2 DVS2 DGD2 INC2 IPC2 REF2 RXT2 AGD2 ENB2 AVS2 OPC2 ONC2 AGD2 SDO2 SDO1 AGD1 ONC1 OPC1 AVS1 ENB1 AGD1 RXT1 REF1 IPC1 INC1 DGD1 Description Digital Supply Pin for Channel 1 Latch Input for Channel 1 Serial Data Input for Channel 1 Clock Input for Channel 1 Clock Input for Channel 2 Serial Data Input for Channel 2 Serial Data Input for Channel 2 Latch Input for Channel 2 Digital Supply Pin for Channel 2 Digital Ground for Channel 2 Negative Input for Channel 2 Positive Input for Channel 2 Reference Voltage for Channel 2 External Bias Setting Resistor Connection for Channel 2 Analog Ground for Channel 2 Chip Enable Pin for Channel 2 Analog Supply Pin for Channel 2 Positive Output for Channel 2 Negative Output for Channel 2 Analog Ground for Channel 2 Serial Data Output for Channel 2 Serial Data Output for Channel 1 Analog Ground for Channel 1 Negative Output for Channel 1 Positive Output for Channel 1 Analog Supply Pin for Channel 1 Chip Enable Pin for Channel 1 Analog Ground for Channel 1 External Bias Setting Resistor Connection for Channel 1 Reference Voltage for Channel 1 Positive Input for Channel 1 Negative Input for Channel 1 Digital Ground for Channel 1
Rev. 0 | Page 7 of 16
07051-002
DGD2 INC2 IPC2 REF2 RXT2 AGD2 ENB2 AVS2
AD8372 TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, TA = 25C, ZS = 150 , ZL = 250 , 1 V p-p differential output, both channels enabled, unless otherwise noted.
40 30
20
OUTPUT REFERRED P1dB (dBm)
19 +25C 18 +85C -40C 17
VOLTAGE GAIN (dB)
20 10 0 -10 -20 -30 1M
16
07051-005
10M
100M
1G
0
10
20
30
40
50
60
70
80
90
FREQUENCY (Hz)
FREQUENCY (MHz)
Figure 5. Gain vs. Frequency by Gain Code (All Codes), Differential In, Differential Out
-60 -65
Figure 8. P1dB, Maximum Gain
180 160 140
9 8 7 6 5 4 3 2 1 0 300000000
HARMONIC DISTORTION (dBc)
-70 -75 HD2 -80 -85 -90 -95 -100 HD3
RESISTANCE ()
120 100 80 60 40 20 0 0 100000000 200000000
07051-006
FREQUENCY (MHz)
50000000
150000000
250000000
FREQUENCY (MHz)
Figure 6. 2nd and 3rd Harmonic Distortion
Figure 9. Input Equivalent Parallel Impedance
100 90 80 70 OIP2 - AV = 32 OIP2 - AV = 10
70 60 50
CMRR (dB)
OIP2/OIP3 (dBm)
60 50 40 30 20 10 OIP3 - AV = 10
OIP2 - AV = -9
40 30 20
OIP3 - AV = 32
OIP3 - AV = -9
10 0
07051-007
0
10
20
30
40
50
60
70
80
90
0
10
20
30
40
50
60
70
80
90
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 7. OIP2 and OIP3
Figure 10. CMRR vs. Frequency
Rev. 0 | Page 8 of 16
07051-010
0
07051-009
0
10
20
30
40
50
60
70
80
90
CAPACITANCE (pF)
07051-008
15
AD8372
50 45 40
NOISE FIGURE (dB)
AV = 0dB
35 30 25 20 15 10 5 0 20 40 60 80 100 120 140 160 180 200
07051-012
AV = 10dB
AV = 20dB
AV = 32dB
07051-011
0
20ns/DIV
FREQUENCY (MHz)
Figure 11. Noise Figure vs. Frequency
Figure 13. AD8372 Response to 6 dB Step Change in Gain (Gain Register Setting 36 to Setting 42); Falling Edge Shown is Serial Clock Input Edge
0 -10 -20 -30 -40 -50 -60 -70 -80
07051-013
(dB)
-90 1M
10M
100M
1G
FREQUENCY (Hz)
Figure 12. Isolation, Input to Opposite Output at Maximum Gain (To calculate output to output gain, subtract 29 dB from this plot)
Rev. 0 | Page 9 of 16
AD8372 THEORY OF OPERATION
The AD8372 is a dual differential variable gain amplifier. Each amplifier consists of a 150 digitally controlled 6 dB attenuator followed by a 1 dB vernier and a fixed gain transconductance amplifier. The differential output on each amplifier consists of a pair of open-collector transistors. It is recommended that each opencollector output be biased to +5 V with a high value inductor. A 33 H inductor, such as the Coilcraft(R) 1812LS-333XJL, is an excellent choice for this component. A 250 resistor should be placed across the differential outputs to provide a current-tovoltage conversion and as a source impedance for passive filtering, post AD8372. The gain for each side is based on a 250 differential load and varies as the RLOAD changes per the following equations: Gain = 20log(RLOAD/250), for voltage gain Gain = 10log(RLOAD/250), for power gain The dependency of the gain on the load is due to the opencollector output stage that is biased using external chokes. The inductance of the chokes and the resistance of the load determine the low frequency pole of the amplifier. The high frequency pole is set by the parasitic capacitance of the chokes and outputs in parallel with the output resistance. The total supply current of 106 mA per side consists of 70 mA for the combined outputs and about 36 mA through the power supply pins. Each side has an external resistor (REXT) to ground to set the transconductance of the output stage. For optimum distortion, 106 mA total current per side is recommended, making the REXT value about 2.0 k. Each side has a 2.4 V reference pin and that same common-mode voltage appears on the inputs. This reference should be decoupled using a 0.1 F capacitor. The part can be powered down to less than 2.6 mA by setting the ENB pin low for the appropriate side. The noise figure of the AD8372 is 7.8 dB at maximum gain and increases as the gain is reduced. The increase in noise figure is equal to the reduction in gain. The linearity of the part measured at the output is first-order independent of the gain setting. Layout considerations should include minimizing capacitance on the outputs by avoiding ground planes under the chokes, and equalizing the output line lengths for phase balance. primarily to the use of differential signaling techniques to cancel various distortion components in the device. In addition, all ac characterization was done using differential signal paths. Using this device with either the input or the output in a singleended circuit significantly degrades the overall performance of the AD8372.
PASSIVE FILTER TECHNIQUES
The AD8372 has a 100 differential input impedance. For optimal performance, the differential output load should be 250 . When designing passive filters around the AD8372, these impedances must be taken into account.
DIGITAL GAIN CONTROL
The digital gain control interface consists of four pins: SDI, SDO, CLK, and LATCH. The interface is active when the LATCH pin is shifted low. Gain words are written into the AD8372 via the SDI pin, and read back from the SDO pin. The first bit clocked into the data input pin determines whether the interface is in write or read mode. The second bit is a don't care bit, while the remaining six bits program the gain. In read mode, the SDO pin clocks out the 6-bit gain word, LSB to MSB. The gain can be programmed between -9 dB and 32 dB in 1 dB steps. Timing details are given in Figure 2 and Figure 3. The gain code table is given in Table 3.
DRIVING ANALOG-TO-DIGITAL CONVERTERS
The AD8372 was designed with the intention of driving high speed, high dynamic range ADCs. The circuit in Figure 14 represents a simplified front end of one-half of the AD8372 dual VGA driving an AD9445 14-bit, 125 MHz analog-to-digital converter. The input of the AD8372 is driven differentially using a 1:3 impedance ratio transformer, which also matches the 150 input resistance to a 50 source. The open-collector outputs are biased through the 33 H inductors and are accoupled from the 142 load resistors that, in parallel with the 2 k input resistance of the ADC, provide a 250 load for gain accuracy. The ADC is ac-coupled from the 142 resistors to negate a dc affect on the input common-mode voltage of the AD9445. Including the series 33 resistors improves the isolation of the AD8372 from the switching currents caused by the ADC input sample and hold. The AD9445 represents a 2 k differential load and requires a 2 V p-p signal when VREF = 1 V for a full-scale output. This circuit provides variable gain, isolation, and source matching for the AD9445. Using this circuit with the AD8372 in a gain of 32 dB (maximum gain), an SFDR performance of 74.5 dBc is achieved at 85 MHz. See Figure 15.
SINGLE-ENDED AND DIFFERENTIAL SIGNALS
The AD8372 was designed to be used by applying differential signals to the inputs and using the differential output drive of the device to drive the next device in the signal chain. The excellent distortion performance of the AD8372 is due
Rev. 0 | Page 10 of 16
AD8372
5V 5V 33H 1:3 50 AC 0.1F 0.1F 0.1F 142 0.1F 33 VIN+ VIN-
AD8372
VGA 0.1F 33H
CKL1 SD01 ENA1
1/2
14-BIT ADC
AD9445
14
0.1F 33 142
5V
07051-018
Figure 14. AD8372 Driving an AD9445 ADC
0 FUND: -1.053dBFS -10 2ND: -74.55dBc -20 3RD: -86.45dBc 4TH: -91.35dBc -30 5TH: -89.57dBc 6TH: -91.15dBc -40 -50 -60
1
SNR: 58.12dBc SNRFS: 59.18dBc THD: -73.99dBc SINAD: 58.01dBc SFDR: 74.73dBc WO SPUR: -85.5dBc NOISE FLOOR: -101.3dB
(dBc)
-70 -80 -90 -100 -110 -120 -130 -140 -150 0 ENCODE: 105MHz SAMPLES: 32768 ANALOG: 19.8766MHz 5 6 4
2 3
FUND LEAK: 100 HARM LEAK: 3 DC LEAK: 6
07051-019
5.25 10.50 15.75 21.00 26.25 31.50 36.75 42.00 47.25 52.50 FREQUENCY (MHz)
Figure 15. 74.5 dB SFDR Performance of the AD8372 Driving the AD9445 ADC
Rev. 0 | Page 11 of 16
AD8372
AD8372 CHAR BD
INC 1 IPC1
AGND A GND
R11 R15 TBD
R0603 R0603
R12 TBD H1-7 H1-15
AGND AGND AGND
H1-1 50 OHMS R47 TBD
C0603
R0603
0
C21 0.1UF
4 6
AGND PR I
C8 50 OHMS R44 0
R0603 R0603
C0603
TBD 0.1UF C17
C0603
DGND
DGND
R31 TBD T2 R2 2.74K W2
R0603 R0603 R0603
R32 TBD
3 2 1
R9
R0603
SE C
H1-3 100 OHMS R35
R0603
75 OHMS 100 OHMS TBD R29 T4 4 6
SEC R0603 AGND PRI AGND R0603
R0603
0 75 OHMS
AGND C0603
0 R16 1NF
C0603 C0603
TBD R39 TBD
R0603 DGND R0603 R0603
C0603
W3
C6 TBD 0.1UF C27 R40 TBD R21 0 H1-15 100 OHMS R30 TBD
R0603 AGND 181 2 AGND C0603 C0603 C0603
10K 0.1UF C11 H1-15 C16 R36 R18 0.1UF C32 TBD
L1 33UH
OPC1 50 OHMS
DGND
R10
A GND
H1-4 0.1UF C25 75 OHMS
AGND
3 2 1
R0603
0
W4
C7
0.1UF C26
TBD 100 OHMS
C0603
ONC1
R0603 C0603
C0603
0.1UF C15
50 OHMS
DGND DGND
L2
181 2
33UH
R8 R43 0 32 31 30 29 28 27 26 25 R22
R0603 DGND
75 OHMS 0.1UF C18
H1-5 0 R23
AGND R0603
AGND
R0603
0
C5 0
R0603
EVALUATION BOARD SCHEMATIC
TBD
DGD1 INC1 IPC1 REF1 RXT1 AGD1 ENB1 AVS 1
C0603
W5
100 OHMS OPC1 ONC1 AGD1 AGND 100 OHMS SDO1 SDO2 AGND 100 OHMS 22 21 20 19 18 17 23 24
DGND DGND
R7
1 DVS1 2 LCH1
H1-11 3 SDI1 4 CLK1 Z1 AD8372 SDO2 AGD2 ONC2 OCP2 100 OHMS
R0603 C0603
R0603
0 SDO1
C4 5 CLK2 6 SDI2
DGND
TBD
C0603
DGND
R6 R14 SDO1
R0603
W6
7 LCH2 8 DVS2 0 R25 0 R24
AGND
H1-10
DGD2 INC2 IPC2 REF2 RXT2 ADG2 ENB2 AVS 2
R46 0
R0603 R0603
R0603
0 H1-6
R0603
W7
C3 9 10 11 12 13 14 15 16 C10 TBD
DGND C0603 DGND
TBD
0
0.1UF C28 R37
TBD 100 OHMS TBD
181 2 R0603
C0603
R28
AGND
DGND
75 OHMS 75 OHMS
AGND AGND
L4
R5
L3
33UH
T3
C0603 181 2
50 OHMS 4
33UH
H1-9 R13 H1-12
R0603
ONC2 0.1UF C29 R26 0
R0603
R0603
0 C22 0.1UF C24 0.1UF
AGND C0603 C0603
C2 C19 0.1UF C9 TBD
C0603
3 2 1
SEC PRI
W8
3 2 1
SE C
PR I
4
DGND R0603
DGND
6
P1 13
H1-12
07051-014
P1 10 P1 11 P1 23 P1 24 P1 12 H1-6 P1 25 AGND
Figure 16. AD8372 Evaluation Board Schematic
SDO2 0 H1-15 R38
C0603 DGND
Rev. 0 | Page 12 of 16
R41 TBD
AGND R0603 C0603
6
TBD
C0603
R27 H1-15 TBD
R0603
DGND
OPC2 TBD 100 OHMS R45 0
C0603 A GND R0603
R4 TBD
R0603 AGND
C23 0.1UF R42 75 OHMS
H1-1 75 OHMS
50 OHMS 0.1UF C14
R0603
0 C20 0.1UF R34 TBD T1
R0603 R0603
C1 R33 TBD R1 2.74K 10K W1 R3 0
AGND AGND R0603
C0603
TBD R17
C0603
C12 R49
R0603
AGND
A GND
C0603
AGND
H1-7 1NF
R0603
H1-13 0
50 OHMS
AGND
50 OHMS R19 R20 TBD
R0603 R0603 AGND AGND
R0603 C0603
0.1UF C13 R48 TBD AGND DGND VDD
TES TLOOP
VSS
TE STLOOP
TBD
R0603
RED H1-13 C33
A GND
ORANGE
INC 2
P1 1 P1 2 H1-3 H1-4 H1-5 H1-6 H1-12 H1-11 H1-10 P1 8 P1 9 H1-9
C34 L5 H1-15 TBD
C1206 AGND 3528
L6 TBD 10UF
AGND C1206
3528
P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 B10 H1-8 P2 B20 AGND B9 H1-7 P2 B19 B8 H1-12 P2 B18 H1-16 B7 H1-11 P2 B17 H1-15 B6 H1-10 P2 B16 H1-3 B5 H1-9 P2 B15 H1-4 P1 7 B4 H1-6 P1 6 P2 B14 H1-5 B3 H1-12 P1 5 P2 B13 H1-6 B2 H1-1 P1 4 P2 B12 H1-14 B1
A1
P2
A11
H1-13 P1 3
AGND
IPC2
P2
B11
H1-13
10UF
DGND
P2
A2
H1-1
P2
A12
H1-14
H1-15 P1 14 P1 15 P1 16 P1 20 P1 21 P1 22 P1 17 P1 18 P1 19
DGND
H1-1
P2
A3
P2
A13
H1-6
P2
A4
P2
A14
H1-5
P2
A5
H1-9
P2
A15
H1-4
P2
A6
H1-10
P2
A16
H1-3
P2
A7
H1-11
P2
A17
H1-15
P2
A8
H1-12
P2
A18
H1-16
P2
A9
H1-7
P2
A19
P2
A10
H1-8
P2
A20
AD8372 OUTLINE DIMENSIONS
5.00 BSC SQ 0.60 MAX 0.60 MAX
25 24 32 1
PIN 1 INDICATOR
PIN 1 INDICATOR TOP VIEW 4.75 BSC SQ
0.50 BSC
EXPOSED PAD (BOTTOM VIEW)
17 16 8
3.25 3.10 SQ 2.95
0.50 0.40 0.30 12 MAX
9
0.25 MIN 3.50 REF
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM
1.00 0.85 0.80
SEATING PLANE
0.30 0.23 0.18
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 17. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm x 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters
ORDERING GUIDE
Model AD8372ACPZ-WP 1 AD8372ACPZ-R71 AD8372-EVALZ1
1
Temperature Range -40C to +85C -40C to +85C
Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ], Waffle Pack 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7" Reel Evaluation Board
Package Option CP-32-2 CP-32-2
Ordering Quantity 1,500
Z = RoHS Compliant Part.
Rev. 0 | Page 13 of 16
AD8372 NOTES
Rev. 0 | Page 14 of 16
AD8372 NOTES
Rev. 0 | Page 15 of 16
AD8372 NOTES
(c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07051-0-11/07(0)
Rev. 0 | Page 16 of 16

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